The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complimentary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors, etc.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode which modulates current between the source and drain regions.
One important step in the manufacture of such devices is the formation of isolation areas to electrically separate electrical devices, or portions thereof, that are closely integrated in the silicon wafer. While the particular structure of a given active device can vary between device types, a MOS-type transistor generally includes source and drain regions and a gate electrode that modulates current flowing in a channel between the source and drain regions. Current should not flow between source and drain regions of adjacent MOS-type transistors. However, during the manufacturing process movement of dopant atoms, for example, of boron, phosphorus, arsenic or antimony, can occur within the solid silicon of the wafer. This movement is referred to as diffusion. The diffusion process occurs at elevated temperatures where there is a concentration gradient between dopant atoms external to the silicon wafer and dopant atoms diffusing into the silicon wafer and is typical in connection with forming p-type and n-type regions of a silicon integrated circuit device.
A technique referred to as "trench isolation" has been used to limit such flow in the silicon. A particular type of trench isolation is referred to as shallow trench isolation (STI). In typical logic applications involving 0.25 micron CMOS technology, STI is used to separate the respective diffusion regions of devices of the adjacent complementary transistors.
For some CMOS logic applications where scaling of the transistor gates is required, gate electrodes are used in connection with a dual-gate process instead of all n+ poly-type gate electrodes, and source/drain regions are salicided using Titanium with gate oxides (dielectrics) being relatively thin (for example, about 45 .ANG.). One such application can involve applying five layers of metal interconnect, with use of Tungsten plugs and chemical mechanical polishing (CMP). A relatively high annealing temperature would typically be used to activate dopants in the polysilicon, while a lower annealing temperature would be used for other aspects of the fabrication including saliciding using Ti and preventing shifts in the threshold voltages V.sub.T of the transistors. A practicable fabrication, however, requires use of as few of these high-temperature processes as possible. Thus, in the above-discussed CMOS logic application, tradeoffs are typically made to address such competing concerns.
In contrast to the above type of logic application, many DRAM applications are more concerned with achieving very high yields, very low leakage junctions in the capacitors, and a relatively thick gate oxide (dielectric) to improve reliability for use with higher gate voltage (Vg) requirements, such as in the case of voltage-boosted word lines connected to the gates. DRAM applications are less concerned with transistor gain and, unlike the logic applications, DRAMs employ a complex, small capacitor that is constructed using a self-aligned contact (SAC).
High performance logic circuitry employs high-gain minimum-length transistors, many levels of interconnects and flatter surfaces to aid photolithography in fabricating the interconnects. Specifications for such logic circuitry require high performance, such as reduced RC (resistance-capacitance) delays realized by using salicide processes, and thick interlevel dielectric layers. Somewhat higher levels of leakage ensuing from salicide processes are tolerated. SACs are rarely used. To continue to scale the transistors in a downward direction, dual gate technology is used with both n-type and p-type devices being surface channel type.
Practicably combining logic circuits with DRAMs in the same integrated circuit, sometimes referred to as embedded DRAM applications, requires a melding of competing processing approaches for logic circuits and DRAM circuits. For instance, DRAM cells are typically all n-channel transistor and are not implemented using surface-type transistor channels.
Embedded DRAMs and other stand-alone circuit applications employ, or would benefit from employing, silicided (N+ or P+) gate electrodes. It is difficult, however, to manufacture silicided gate electrodes without undesirable levels of lateral diffusion of the dopants in the silicide formed over the gates. Too much lateral diffusion results in counter doping, thereby resulting in deficient operation of the transistor. This diffusion problem is prevalent in Tungsten-silicided gate electrodes, but can occur in all silicided gates.
With the demands for increasing the density of such MOS-based circuits continuing to escalate, there is an ongoing need to reduce the amount of real estate consumed by various aspects of the circuits and to minimize the complexities and deficiencies resulting from manufacturing processes.